Content addressable memory (CAM) devices are often used in network switching and routing applications to determine forwarding destinations for data packets. A CAM device can be instructed to compare a selected portion of an incoming packet, typically a destination field within the packet header, with data values, called CAM words, stored in an associative storage array within the CAM device. If the destination field matches a CAM word, the CAM device generates a match address that identifies the location of the matching CAM word within the storage array, and asserts a match flag to signal the match. The match address is then typically used to index another storage array, either within or separate from the CAM device, to retrieve a destination address or other routing information for the packet.
FIG. 1 illustrates a portion of a prior-art CAM device 100, including an associative storage array 101 and comparand driver 103. The associative storage array 101, commonly referred to as a CAM array, is populated with CAM cells 12 arranged in rows and columns. Precharged match lines (ML) are coupled to respective rows of the CAM cells, and bit line pairs (BL and /BL) and compare line pairs (CL and /CL) are coupled to respective columns of the CAM cells. Collectively, the bit line pairs form a data port for read/write access to address-selected rows of CAM cells, and the compare line pairs form a compare port for inputting comparand values to the CAM array 101 during compare operations. The CAM cells themselves are specialized store-and-compare circuits each having a storage element to store a constituent bit of a CAM word presented on the bit lines and a compare circuit for comparing the stored bit with a comparand bit presented on the compare lines. In a typical arrangement, the compare circuits within the CAM cells of a given row are coupled in parallel to the match line for the row, with each compare circuit switchably forming a discharge path to discharge the match line if the stored bit and comparand bit do not match. By this arrangement, if any one bit of a CAM word does not match the corresponding bit of the comparand value, the match line for the row is discharged to signal the mismatch condition. If all the bits of the CAM word match the corresponding bits of the comparand value, the match line remains in its precharged state to signal a match. Because a comparand value is presented to all the rows of CAM cells in each compare operation, a rapid, parallel search for a matching CAM word is performed.
Still referring to FIG. 1, an expanded view of a prior-art CAM cell 12 is shown at 112. The CAM cell 12 includes a bi-stable storage circuit 117 (MEM) coupled to a compare circuit 119. The compare circuit 119 includes two pairs of transistors T1/T2 and T3/T4, each coupled in series between a match line (ML) and ground. Gate terminals of transistors T1 and T3 are coupled to the compare lines CL and /CL to receive a comparand bit, C, and complement comparand bit, /C, respectively, and gate terminals of transistors T4 and T2 are coupled to non-inverting and inverting inputs of the storage circuit 117 to receive a data bit, D, and complement data bit, /D, respectively. By this arrangement, when the comparand bit and data bit do not match (i.e., C=0, D=1 or C=1, D=0), a path between the match line and ground is formed between one of the series-coupled transistor pairs, T1/T2 or T3/T4, thereby discharging the match line to signal the mismatch condition. By contrast, if the comparand bit matches the data bit, at least one transistor in each series-coupled transistor pair, T1/T2 and T3/T4, will be switched off so that the match line is isolated from ground within the CAM cell.
Advances in CAM design and semiconductor process technology have enabled increased storage density and compare throughput in each new generation of CAM devices, with modern devices having several hundred thousand CAM cells and the ability to perform hundreds of millions of searches per second, or more. As storage density and compare throughput increase, however, so do power consumption and heat generation. Thermal constraints have emerged as a potentially limiting factor in meeting demands for increased storage density and compare throughput in future generations of CAM devices.
The circuits that charge and discharge the relatively high-capacitance match lines and compare lines are typically the dominant power consumers within a modern CAM device, consuming up to 70% or more of the total power budget. Referring to the prior-art CAM device 100, for example, at the completion of each compare operation, all the compare lines are discharged to enable the match lines to be precharged in preparation for the next compare operation. Then, at the start of the next compare operation, the compare line drivers 103 drive each pair of compare lines to complementary high and low states according to the state of the corresponding bit of comparand value 102. Thus, half the compare lines transition from low to high logic states during each compare operation; a substantial power consumption that increases with compare cycle frequency. A secondary effect of the compare line transitions is a dynamic, capacitive loading of the match lines which, in turn, causes the precharged level of the match lines to temporarily drop (i.e., glitch). Referring to the detailed view of CAM cell 12, for example, if compare lines CL and /CL are initially discharged (i.e., to enable the match line, ML, to be precharged), and transistor T4 is switched off (i.e., D=0), then the isolated drain of transistor T4 will float between logic low and high voltages. Consequently, if comparand line /CL is transitioned to a logic high state in the ensuing compare operation (i.e., C=0; a match condition), then a small charging current will flow through transistor T3 to charge the floating drain node of transistor T4 to a logic high level. A corresponding charging current flows through transistor T1 to charge the floating drain node of transistor T2 when D=C=1. Thus, in a match condition, the drain node of transistor T2 or transistor T4 constitutes a parasitic capacitance, illustrated in the detail view 112 by dashed capacitor symbols, which is charged by a small, parasitic current drawn from the match line. If a mismatch occurs within a cell within a given CAM row (i.e., row of CAM cells), the match line is discharged in any event, so that any parasitic currents drawn by other CAM cells within the same CAM row are largely inconsequential. In a match condition within a CAM row, however, a combined parasitic current equal to the average individual parasitic current multiplied by the number of CAM cells per row (i.e., the width of the row) is drawn from the match line, producing in the aforementioned drop in match line voltage. As the match line is used to signal a match or mismatch within the corresponding row of CAM cells, the transient drop in match line voltage may result in a false mismatch detection (i.e., CAM device should have detected and signaled a match, but does not) and ultimately, non-delivery of a packet or other system-level failure. Historically, such match line glitches have been addressed either by providing additional match line settling time (undesirably reducing compare throughput of the CAM device), or by applying additional match line precharge current to counteract the transient voltage drop, the latter solution further increasing the power consumption within the CAM device.